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asahi kasei [ak4641] ms0301-e-00 2004/05 - 1 - general description the ak4641 is targeted at pda and other low-power, small size applications. it features a 16bit stereo codec with a built-in microphone-amplifier and 16 bit mono codec for bluetooth interface. input circuits include microphone-amplifier and alc (auto level control) circuit. the ak4641 is available in a 36pin qfn, utilizing less board space than competitive offerings. features 1. recording function of 16bit stereo codec ? mono input ? 2 to 1 selector (internal and external mic) ? 1 st mic amplifier: +20db or 0db ? 2 nd amplifier with alc: +27.5db ? 8db, 0.5db step ? adc performance: s/(n+d): 81db, s/n: 86db ? sampling rate: 7khz 48khz ? audio interface format: i 2 s, 16bit msb justified 2. playback function of 16bit stereo codec ? digital de-emphasis filter (tc=50/15 s, fs=32khz, 44.1khz, 48khz) ? digital volume (0db ? 127db, 0.5db step, mute) ? 5 band equalizer ? stereo line output - performance: s/(n+d): 86db, s/n: 90db ? mono line output - differential output - performance: s/(n+d): 86db, s/n: 93db ? aux input - differential input - +24db ? 21db, 3db step ? sampling rate: 7khz 48khz ? audio interface format: i 2 s, 16bit msb justified, 16bit lsb justified 3. 16bit mono codec ? analog mix path for bluetooth interface ? sample rate: 8khz 16khz ? audio interface format: short/long frame, i 2 s, 16bit msb justified 4. power management 5. master clock: 1.792mhz 12.288mhz 6. control mode: i 2 c bus 7. ta = ? 10 70 c 8. power supply: 2.6v 3.6v (typ. 3.3v) 9. power supply current: 17ma 10. package: 36pin qfn (0.5mm pitch) ak4641 16-bit ? codec with bluetooth interface
asahi kasei [ak4641] ms0301-e-00 2004/05 - 2 - ? block diagram alc1 (ipga) pmmic att avdd avss micout ain lrck bick sdto sdti pdn dsp and up vcom lout rout auxin+ control register stereo codec audio interface scl sda volume pmlo pmmo pmmix mout+ att mclk pmaux mpe mic power supply mdt 0.075 x avdd ext int mic-amp 0db or 20db mpi mic power supply hpf adc pmadc pmdac datt smute dac att 5band eq mono codec audio i/f pll bbick bsync bsdto bsdti vcoc pmad2 bluetooth module dvdd dvss dac mout2 pmmo2 bvdd bvss pmda2 auxin- mout- tst2 tst1 hpf adc figure 1. block diagram
asahi kasei [ak4641] ms0301-e-00 2004/05 - 3 - ? ordering guide ak4641vn ? 10 +70 c 36pin qfn (0.5mm pitch) AKD4641 evaluation board for ak4641 ? pin layout (36pin qfn) mpe mpi int vcom a vss a vdd bvdd bvss vcoc ext mdt micout a in a uxin+ a uxin ? mout+ mout ? pdn tst1 scl sda sdti sdto lrck bick mclk rout mout2 tst2 bbick bsync bsdto bsdti dvss dvdd top view 1 2 3 4 5 6 7 8 9 36 35 34 10 27 26 25 24 23 22 21 20 19 lout 33 32 31 30 29 28 11 12 13 14 15 16 17 18
asahi kasei [ak4641] ms0301-e-00 2004/05 - 4 - pin/function no. pin name i/o function 1 mpe o mic power supply pin for external microphone 2 mpi o mic power supply pin for internal microphone 3 int i internal microphone input pin (mono input) 4 vcom o common voltage output pin, 0.45*avdd bias voltage of adc inputs and dac outputs. 5 avss - analog ground pin 6 avdd - analog power supply pin 7 bvdd - power supply pin for 16bit mono codec of bluetooth i/f 8 bvss - ground pin for 16bit mono codec of bluetooth i/f 9 vcoc o pll loop filter pin for 16bit mono codec of bluetooth i/f 10 pdn i power-down mode pin ?h?: power up, ?l?: power down reset and initializes the control register. 11 tst1 i test pin. connect to dvss. 12 scl i control data clock pin 13 sda i/o control data input pin 14 sdti i audio serial data input pin 15 sdto o audio serial data output pin 16 lrck i input/output channel clock pin 17 bick i audio serial data clock pin 18 mclk i external master clock input pin 19 dvdd - digital power supply pin 20 dvss - digital ground pin 21 bsdti i serial data input pin for 16bit mono codec of bluetooth i/f 22 bsdto o serial data output pin for 16bit mono codec of bluetooth i/f 23 bsync i sync signal pin for 16bit mono codec of bluetooth i/f 24 bbick i serial data clock pin for 16bit mono codec of bluetooth i/f 25 tst2 i test pin. connect to avss. 26 mout2 o mono line output 2 pin 27 rout o rch stereo line output pin 28 lout o lch stereo line output pin 29 mout ? o mono line negative output pin 30 mout+ o mono line positive output pin 31 aux in ? i mono aux negative input pin 32 aux in+ i mono aux positive input pin 33 ain i analog input pin 34 micout o microphone analog output pin 35 mdt i microphone detect pin (internal pull down by 500k ? ) 36 ext i external microphone input pin (mono input) note: all input pins except analog input pins (int, ext, ain, auxin+, auxin ? , mdt) should not be left floating. ? handling of unused pin the unused i/o pins should be processed appropriately as below. classification pin name setting analog input int, auxin+, auxin ? , ain, mdt, ext these pins should be open. analog output mpe, mpi, mout2, rout, lout, mout ? , mout+, micout these pins should be open. digital input bsdti, bsync, bbick these pins should be connected to dvss. digital output bsdto these pins should be open.
asahi kasei [ak4641] ms0301-e-00 2004/05 - 5 - absolute maximum ratings (avss, dvss, bvss =0v; note 1) parameter symbol min max units power supplies: analog avdd ? 0.3 4.6 v digital dvdd ? 0.3 4.6 v 16bit mono codec bvdd ? 0.3 4.6 v |avss ? dvss| (note 2) ? gnd1 - 0.3 v |avss ? bvss| (note 2) ? gnd2 - 0.3 v input current, any pin except supplies iin - 10 ma analog input voltage vina ? 0.3 avdd+0.3 v digital input voltage vind ? 0.3 dvdd+0.3 v ambient temperature (powered applied) ta ? 10 70 c storage temperature tstg ? 65 150 c note 1. all voltages with respect to ground. note 2. avss, dvss and bvss must be connected to the same analog ground plane. warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. recommended operating conditions (avss, dvss, bvss=0v; note 1) parameter symbol min typ max units power supplies analog avdd 2.6 3.3 3.6 v (note 3) digital dvdd 2.6 3.3 3.6 v 16bit mono codec bvdd 2.6 3.3 3.6 v differences avdd ? bvdd ? 0.1 0 +0.1 v avdd ? dvdd ? 0.3 0 +0.3 v bvdd ? dvdd ? 0.3 0 +0.3 v note 1. all voltages with respect to ground. note 3. the power up sequence between avdd, dvdd and bvdd is not critical. * akm assumes no responsibility for the usag e beyond the conditions in this datasheet.
asahi kasei [ak4641] ms0301-e-00 2004/05 - 6 - analog characteristics (ta=25 c; avdd=dvdd=bvdd=3.3v; avss=dvss=bvss=0v; signal frequency=1khz; 16bit data; stereo codec: fs=44.1khz, bick=64fs; measurement frequency=20hz 20khz; mono codec: bfs=8khz; bbick=32bfs; measurement frequency=20hz 3.4khz; unless otherwise specified) parameter min typ max units mic amplifier input resistance 20 30 40 k ? mgain bit = ?0? - 0 - db gain mgain bit = ?1? - +20 - db mic power supply output voltage (note 4) 2.22 2.47 2.72 v load resistance 2 - - k ? load capacitance - - 30 pf mic detection comparator voltage level (note 5) 0.165 - 0.257 v internal pull down resistance 250 500 750 k ? input pga characteristics: input resistance (note 6) 5 10 15 k ? step size 0.1 0.5 0.9 db max (ipga6-0 bits = ?47h?) - +27.5 - db gain control range min (ipga6-0 bits = ?00h?) - ? 8 - db adc analog input characteristics of stereo codec: mic gain=+20db, ipga=0db, alc1=off, mic ipga adc of stereo codec resolution - - 16 bits input voltage (mic gain=+20db, note 7) 0.168 0.198 0.228 vpp s/(n+d) ( ? 1dbfs) 71 81 - db d-range ( ? 60dbfs, a-weighted) 78 86 - db mic gain=+20db, a-weighted 78 86 - db s/n mic gain=0db, a-weighted - 92 - db dac characteristics of stereo codec: resolution - - 16 bits stereo line output characteristics: r l =10k ? , dac of stereo codec lout/rout pins output voltage (note 8) 1.78 1.98 2.18 vpp s/(n+d) (0dbfs) 76 86 - dbfs s/n (a-weighted) 82 90 - db interchannel isolation - 100 - db interchannel gain mismatch - 0.1 0.5 db load resistance 10 - - k ? load capacitance - - 30 pf note 4. output voltage is proportional to avdd voltage. vout = 0.75 x avdd (typ). note 5. comparator voltage level is proportional to avd d voltage. vout = 0.05 x avdd (min), 0.078 x avdd (max). note 6. when ipga gain is changed, this typical value changes between 8k ? and 11k ? . note 7. input voltage is proportional to avdd voltage. vin = 0.06 x avdd (typ). note 8. output voltage is proportional to avdd voltage. vout = 0.6 x avdd (typ).
asahi kasei [ak4641] ms0301-e-00 2004/05 - 7 - parameter min typ max units mono line output characteristics: r l =20k ? , dac of stereo codec mout+/mout ? pins mogn bit = ?1?, ? 17db - 0.305 - vpp output voltage (note 9) mogn bit = ?0?, +6db 3.56 3.96 4.36 vpp mogn bit = ?1?, ? 17db - 74 - dbfs s/(n+d) (0dbfs) mogn bit = ?0?, +6db 76 86 - dbfs mogn bit = ?1?, ? 17db - 77 - db s/n (a-weighted) mogn bit = ?0?, +6db 83 93 - db mogn bit = ?1?, ? 17db 2 - - k ? load resistance mogn bit = ?0?, +6db 20 - - k ? load capacitance - - 30 pf aux input: auxin+, auxin ? pins: auxsi bit = ?0? maximum input voltage (note 10) - 1.98 - vpp input resistance 25 40 55 k ? step size 1 3 5 db max (gn3-0 bits = ?fh?) - +24 - db gain control range min (gn3-0 bits = ?0h?) - ? 21 - db mono output: r l =10k ? , dac of stereo codec mix mout2 pin output voltage (note 11) 1.78 1.98 2.18 vpp s/(n+d) (0dbfs) 76 86 - db s/n (a-weighted) 83 93 - db load resistance 10 - - k ? load capacitance (note 12) - - 30 pf 16bit mono adc analog input characteristics: auxin pin mix adc of mono codec: aux volume = 0db resolution - - 16 bits input voltage (note 13) 1.68 1.98 2.28 vpp s/(n+d) ( ? 1dbfs) 65 75 - db s/n 79 89 - db 16bit mono dac analog output characteristics: dac of mono codec mout+/ ? pins: mogn = +6db resolution - - 16 bits output voltage (note 14) 3.56 3.96 4.36 vpp s/(n+d) 68 78 - db s/n 82 92 - db power supplies power up (pdn pin = ?h?) avdd+dvdd+ bvdd - 17 27 ma power down (pdn pin = ?l?) (note 15) avdd+dvdd+bvdd - - 100 a note 9. output voltage is proportional to avdd voltage. vout = 1.2 x avdd (typ) @mogn bit = ?0?, 0.092 x avdd (typ) @mogn bit = ?1? at differential output. note 10. maximum input voltage is proportional to avdd voltage. vin = (auxin+) ? (auxin ? ) = 0.6 x avdd (typ) at auxsi bit = ?0?, vin = auxin+ = 0.6 x avdd (typ) at auxsi bit = ?1?. note 11. output voltage is proportional to avdd voltage. vout = 0.6 x avdd (typ). note 12. when the output pin drives a capacitive load, a resistor should be added in series between the output pin and capacitive load. note 13. input voltage is proportional to avdd voltage. vin = 0.6 x avdd (typ). note 14. output voltage is proportional to avdd voltage. vout = 0.6 x avdd (typ). note 15. all digital input pins are fixed to dvss. when the voltage difference among dvdd, bvdd and avdd is larger than 0.3v, the power supply current at power down mode increases.
asahi kasei [ak4641] ms0301-e-00 2004/05 - 8 - filter characteristics (stereo codec) (ta= ? 10 70 c; avdd, dvdd, bvdd=2.6 3.6v; fs=44.1khz; dem=off) parameter symbol min typ max units adc digital filter (decimation lpf): passband (note 16) 0.1db pb 0 - 17.4 khz ? 1.0db - 20.0 - khz ? 3.0db - 21.1 - khz stopband sb 25.7 - - khz passband ripple pr - - 0.1 db stopband attenuation sa 68 - - db group delay (note 17) gd - 17.0 - 1/fs group delay distortion ? gd - 0 - s adc digital filter (hpf): frequency response ? 3.0db fr - 3.4 - hz (note 16) ? 0.5db - 10 - hz ? 0.1db - 22 - hz dac digital filter: passband (note 16) 0.1db pb 0 - 19.6 khz ? 0.7db - 20.0 - khz ? 6.0db - 22.05 - stopband sb 25.2 - - khz passband ripple pr - - 0.01 db stopband attenuation sa 59 - - db group delay (note 17) gd - 17.9 - 1/fs dac digital filter + scf: frequency response: 0 20.0khz fr - 1.0 - db note 16. the passband and stopband frequencies scale with fs (system sampling rate). for example, adc is pb=0.454*fs (@-1.0db), dac is pb=0.454*fs (@-0.01db). note 17. the calculated delay time caused by digital filtering. this time is from the input of analog signal to setting of the 16bit data of both channels from the input register to the output register of the adc. this time includes the group delay of the hpf. for the dac, this time is from setting the 16bit data of both channels from the input register to the output of analog signal.
asahi kasei [ak4641] ms0301-e-00 2004/05 - 9 - filter characteristics (16bit mono codec) (ta= ? 10 70 c; avdd, dvdd, bvdd=2.6 3.6v; bfs=8khz) parameter symbol min typ max units adc digital filter (decimation lpf): passband (note 16) 0.1db pb 0 - 3.1 khz ? 1.0db - 3.6 - khz ? 3.0db - 3.8 - khz stopband sb 4.7 - - khz passband ripple pr - - 0.1 db stopband attenuation sa 68 - - db group delay (note 17) gd - 17.0 - 1/bfs group delay distortion ? gd - 0 - s adc digital filter (hpf): frequency response ? 3.0db fr - 0.62 - hz (note 16) ? 0.5db - 1.81 - hz ? 0.1db - 3.99 - hz dac digital filter: passband (note 16) 0.1db pb 0 - 3.6 khz ? 0.7db - 3.6 - khz ? 6.0db - 4.0 - stopband sb 4.6 - - khz passband ripple pr - - 0.01 db stopband attenuation sa 59 - - db group delay (note 17) gd - 15.8 - 1/bfs dac digital filter + scf: frequency response: 0 20.0khz fr - 1.0 - db note 16. the passband and stopband frequencies scale with fs (system sampling rate). for example, adc is pb=0.454*bfs (@-1. 0db), dac is pb=0.454*bfs (@-0.01db). note 17. the calculated delay time caused by digital filtering. this time is from the input of analog signal to setting of the 16bit data of both channels from the input register to the output register of the adc. this time includes the group delay of the hpf. for the dac, this time is from setting the 16bit data of both channels from the input register to the output of analog signal.
asahi kasei [ak4641] ms0301-e-00 2004/05 - 10 - dc characteristics (ta= ? 10 70 c; avdd, dvdd, bvdd=2.6 3.6v) parameter symbol min typ max units high-level input voltage vih 70%dvdd - - v low-level input voltage vil - - 30%dvdd v input voltage at ac coupling (note 18) vac 50%dvdd - - v high-level output voltage (iout= ? 200 a) voh dvdd ? 0.2 - - v low-level output voltage (except sda pin: iout=200 a) vol - - 0.2 v (sda pin: iout=3ma) vol - - 0.4 v input leakage current iin - - 10 a note 18. the external clock is input to mclk pin via ac coupled capacitor. switching characteristics (ta= ? 10 70 c; avdd, dvdd, bvdd=2.6 3.6v; c l =20pf) parameter symbol min typ max units 16bit stereo codec interface timing: master clock timing (mclk pin) frequency fclk 1.792 - 12.288 mhz pulse width low tclkl 0.4/fclk - - ns pulse width high tclkh 0.4/fclk - - ns ac pulse width (note 19) tacw 0.4/fclk - - ns lrck timing frequency fs 7 - 48 khz duty cycle duty 45 - 55 % audio interface timing bick period tbck 312.5 - - ns bick pulse width low tbckl 130 - - ns pulse width high tbckh 130 - - ns lrck edge to bick ? ? (note 20) tlrb 50 - - ns bick ? ? to lrck edge (note 20) tblr 50 - - ns lrck to sdto (msb) (except i 2 s mode) tlrs - - 80 ns bick ? ? to sdto tbsd - - 80 ns sdti hold time tsdh 50 - - ns sdti setup time tsds 50 - - ns note 19. refer to figure 3. note 20. bick rising edge must not occur at the same time as lrck edge.
asahi kasei [ak4641] ms0301-e-00 2004/05 - 11 - parameter symbol min typ max units 16bit mono codec interface timing: sync timing frequency (pll lock range) bfs 8 - 16 khz serial interface timing at short/long frame sync bbick frequency fbbck 128 2048 khz bbick period tbbck 488 ns bbick duty cycle tbdut 50 % bbick pulse width low tbbckl 200 ns pulse width high tbbckh 200 ns bsync edge to bbick ? ? tbsyb 50 ns bbick ? ? to bsync edge tbbsy 50 ns bsync to bsdto (msb) (except short frame) tbsyd 80 ns bbick ? ? to bsdto tbbsd 80 ns bsdti hold time tbsdh 50 ns bsdti setup time tbsds 50 ns bsync pulse width low tbbsl 3300 ns pulse width high tbbsh 440 ns serial interface timing at msb justified and i 2 s bbick frequency fbbck 256 2048 khz bbick period tbbck 488 ns bbick duty cycle tbdut 50 % bbick pulse width low tbbckl 200 ns pulse width high tbbckh 200 ns bsync edge to bbick ? ? tbsyb2 50 ns bbick ? ? to bsync edge tbbsy2 50 ns bsync to bsdto (msb) (except i 2 s mode) tbsyd2 80 ns bbick ? ? to bsdto tbbsd2 80 ns bsdti hold time tbsdh2 50 ns bsdti setup time tbsdh2 50 ns bsync duty cycle bduty2 45 50 55 % control interface timing (i 2 c bus mode): scl clock frequency fscl - 400 khz bus free time between transmissions tbuf 1.3 - s start condition hold time (prior to first clock pulse) thd:sta 0.6 - s clock low time tlow 1.3 - s clock high time thigh 0.6 - s setup time for repeated start condition tsu:sta 0.6 - s sda hold time from scl falling (note 21) thd:dat 0 - s sda setup time from scl rising tsu:dat 0.1 - s rise time of both sda and scl lines tr - 0.3 s fall time of both sda and scl lines tf - 0.3 s setup time for stop condition tsu:sto 0.6 - s pulse width of spike noise suppressed by input filter tsp 0 50 ns reset timing pdn pulse width (note 22) tpd 150 ns pmadc ? ? to sdto valid (note 23) tpdv 2081 1/fs pmad2 ? ? to bsdto valid (note 24) tbpdv 1057 1/bfs note 21. data must be held long enough to bridge the 300ns-transition time of scl. note 22. the ak4641 can be reset by the pdn pin = ?l?. note 23. this is the count of lrck ? ? from the pmadc bit = ?1?. note 24. this is the count of bsync ? ? from the pmad2 bit = ?1?. purchase of asahi kasei microsystems co., ltd i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system, provided the system conform to the i 2 c specifications de fined by philips.
asahi kasei [ak4641] ms0301-e-00 2004/05 - 12 - ? timing diagram 1/fclk mclk tclkh tclkl vih vil 1/fs lrck vih vil tbck bick tbckh tbckl vih vil figure 2. clock timing of stereo codec mclk input monitoring point dvss tacw t acw dvss 1/fclk 1000pf 100k ? vac note. this circuit shows how to monitor mclk ac coupling timing. this circuit is not used in actual system. figure 3. mclk ac coupling timing
asahi kasei [ak4641] ms0301-e-00 2004/05 - 13 - lrck vih vil tblr bick vih vil tlrs sdto 50%dvdd tlrb tbsd tsds sdti vil tsdh vih figure 4. audio interface timing of stereo codec 1/bfs vih vil bsync tbbsl tbbsh tbbck tbbckl vih tbbckh vil bbick figure 5. clock timing of 16bit mono codec
asahi kasei [ak4641] ms0301-e-00 2004/05 - 14 - tbsyb bsync vih bbick vil bsdto 50%dvdd tbbsd vih vil tbbsy tbsds bsdti vih vil tbsdh tbsyd figure 6. 16bit mono codec interface timing at short and long frame sync tbsyb2 bsync vih bbick vil bsdto 50%dvdd tbbsd2 vih vil tbbsy2 tbsds2 bsdti vih vil tbsdh2 tbsyd2 figure 7. 16bit mono codec interface timing at msb justified and i 2 s
asahi kasei [ak4641] ms0301-e-00 2004/05 - 15 - stop start start stop thigh thd:dat sda scl tbuf tlow tr tf tsu:dat vih vil thd:sta tsu:sta vih vil tsu:sto tsp figure 8. i 2 c bus mode timing pmadc bit tpdv sdto 50%dvdd figure 9. power down & reset timing 1 pmad2 bit tbpdv bsdto 50%dvdd figure 10. power down & reset timing 2 tpd pdn vil figure 11. power down & reset timing 3
asahi kasei [ak4641] ms0301-e-00 2004/05 - 16 - operation overview ? system clock input the ak4641 requires a master clock (mclk). this master clock is input to the ak4641 by inputting an external cmos-level clock to the mclk pin or by inputting an external clock that is greater than 50% of the dvdd level to the mclk pin through a capacitor. mckpd and mckac bits shoul d be set as shown in table 1. adc and dac of 16bit stereo codec are powered-down at mckpd bit = ?1?. master clock status mckac bit mckpd bit external clock direct input (figure 12) clock is input to mclk pin. 0 0 clock is not input to mclk pin. 0 1 ac coupling input (figure 13) clock is input to mclk pin. 1 0 clock is not input to mclk pin. 1 1 table 1. mckpd and mckac bits setting for master clock status (1) external clock direct input mclk ak4641 mckpd bit = "0" external clock mckac bit = "0" figure 12. external master clock input block (2) ac coupling input mclk ak4641 mckpd bit = "0" external clock mckac bit = "1" 0.1uf figure 13. external clock mode (input: 50%dvdd)
asahi kasei [ak4641] ms0301-e-00 2004/05 - 17 - the clock required to operate are mclk, lrck (fs) and bick ( 32fs). then the master clock (mclk) should be synchronized with lrck. the phase between these clocks does not matter. the s/n of the dac of stereo codec at low sampling frequencies is worse than at high sampling frequencies due to out-of-band noise. the out-of-band noise can be improved by us ing higher frequency of the master clock. the s/n of the dac output of stereo codec through headphone amp at fs=8khz is shown in table 3. mck1 mck0 sampling frequency (fs) mclk 0 0 7khz 48khz 256fs default 0 1 7khz 24khz 512fs 1 0 7khz 12khz 1024fs 1 1 - n/a table 2. select master clock frequency mclk s/n (fs=8khz, a-weighted) 256fs 82db 512fs 90db 1024fs 90db table 3. relationship between mclk and s/n of line out when the synchronization is out of phase by changing th e clock frequencies during normal operation, the ak4641 may occur pop noise. all external clocks (mclk, bick and lrck) should always be present when either adc or dac of stereo codec is power-up. if these clocks are not provided, the ak4641 may draw excess current and it is not possible to operate properly because utilizes dynamic refreshed logic internally. if the ex ternal clocks are not present, the ak4641 should be in the power-down mode. power up power down bick pin input fixed to ?l? or ?h? externally lrck pin input fixed to ?l? or ?h? externally table 4. clock operation ? system reset upon power-up, reset the ak4641 by bringing the pdn pin = ?l?. this ensures that all internal registers are reset to their initial values. the adc of stereo codec enters an initialization cycle that starts when the pmadc bit is changed from ?0? to ?1?. the initialization cycle time is 2081/ fs, or 47.2ms@fs=44.1khz. during the initializa tion cycle, the adc di gital data output of stereo codec is forced to a 2's compliment, ?0?. the adc output of stereo codec reflects the analog input signal after the initialization cycle is complete. the dac of stereo codec does not require an initialization cycle. the adc of mono codec enters an initialization cycle that starts when the pmad2 bit is changed from ?0? to ?1?. the initialization cycle time is 1057/bfs, or 132ms@bfs=8khz. during the initialization cycle, the adc digital data output of mono codec is forced to a 2's compliment, ?0?. the adc output of mono codec reflects the analog input signal after the initialization cycle is complete. the dac of mono codec does not require an initialization cycle.
asahi kasei [ak4641] ms0301-e-00 2004/05 - 18 - ? audio interface format of stereo codec three types of data formats are available and are selected by setting the dif1-0 bits. in all modes, the serial data is msb first, 2?s complement format. the sdto is clocked out on the falling edge of bick and the sdti is latched on the rising edge. lrck and bick must be input to the ak4641 in slave mode. if 16bit data that adc of stereo codec outputs is converted to 8bit data by removing lsb 8bit, ? ? 1? at 16bit data is converted to ? ? 1? at 8bit data. and when the dac of stereo codec playbacks this 8bit data, ? ? 1? at 8bit data will be converted to ? ? 256? at 16bit data and this is a large offset. this offset can be removed by adding the offset of ?128? to 16bit data before converting to 8bit data. mode dif1 dif0 sdto (adc) sdti (dac) bick figure 0 0 0 msb justified lsb justified 32fs figure 14 1 0 1 msb justified msb justified 32fs figure 15 2 1 0 i 2 s i 2 s 32fs figure 16 default 3 1 1 n/a n/a n/a - table 5. audio interface format of stereo codec lrck bick(32fs) sdto(o) sdti(i) 0 15 14 15 14 110 13 13 23 7 76543 210 6543 10 2 9 1112131415 0 12 3 15 14 13 1 0 15 15 76543 210 10 9 1112131415 bick(64fs) 0 116 2 3 17 18 31 0 1 2 3 1 0 16 17 18 31 sdto(o) sdti(i) 15 14 13 don't care 10 1 15 15 210 15 0 15 14 15 14 don't care 15:msb, 0:lsb lch data rch data figure 14. mode 0 timing
asahi kasei [ak4641] ms0301-e-00 2004/05 - 19 - lrck bick(32fs) sdto(o) sdti(i) 0 15 14 15 14 110 13 13 23 7 76543 210 6543 10 2 9 1112131415 0 12 3 15 14 13 1 0 15 15 76543 210 10 9 1112131415 bick(64fs) 0 116 2 3 17 18 31 0 1 2 3 1 0 16 17 18 31 sdto(o) sdti(i) 15 14 13 don't care 1 15 15 15 0 15 14 15 14 don't care 15:msb, 0:lsb lch data rch data 13 10 13 10 15 figure 15. mode 1 timing lrck bick(32fs) sdto(o) sdti(i) 0 15 14 15 14 110 23 7 76543 210 6543 10 2 9 1112131415 0 12 3 15 14 1 0 76543 210 10 9 1112131415 bick(64fs) 0 116 2 3 17 18 31 0 1 2 3 1 0 16 17 18 31 sdto(o) sdti(i) 15 14 don't care 2 15 1 15 15 15 don't care 15:msb, 0:lsb lch data rch data 14 21 14 21 8 8 8 0 0 0 0 figure 16. mode 2 timing
asahi kasei [ak4641] ms0301-e-00 2004/05 - 20 - ? audio interface format of mono codec four types of data formats are available for 16bit mono codec and are selected by setting the btfmt1-0 bits. in all modes, the serial data is msb first, 2?s complement format. in short frame sync and long frame sync modes, the bsdto is clocked out on the rising edge of bbick and the bsdti is latched on the falling edge. in msb justified and i 2 s modes, the bsdto is clocked out on the falling edge of bbick and the bsdti is latched on the rising edge. bsync and bbick must be input to the ak4641. mode btfmt1-0 bbick figure short frame sync 00 16bfs figure 17 default long frame sync 01 16bfs figure 18 msb justified 10 32bfs figure 19 i 2 s 11 32bfs figure 20 table 6. audio interface format for 16bit mono codec (1) short frame sync bsdti bsdto bbick bsync d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 don?t care don?t care d15 d14 d15 d14 1/bfs d15 d14 d15 d14 figure 17. timing of short frame sync (2) long frame sync don?t care bsdti bsdto bbick bsync d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 don?t care d15 d14 d15 d14 1/bfs d13 d13 d15 d14 d15 d14 figure 18. timing of long frame sync
asahi kasei [ak4641] ms0301-e-00 2004/05 - 21 - (3) msb justified bsync bbick (32bfs) bsdto(o) bsdti(i) 0 15 14 15 14 110 13 13 23 7 76543 210 6543 10 2 9 1112131415 0 12 3 1 0 15 15 10 9 1112131415 bbick (64bfs) 0 116 2 3 17 18 31 0 1 2 3 1 0 16 17 18 31 bsdto(o) bsdti(i) 15 14 13 don't care 1 15 15 0 15 14 15 don't care 15:msb, 0:lsb 13 10 15 don't care don't care figure 19. timing of msb justified (4) i 2 s bsync bbick (32bfs) bsdto(o) bsdti(i) 0 15 14 15 14 110 23 7 76543 210 6543 10 2 9 1112131415 0 12 3 1 0 10 9 1112131415 bbick (64bfs) 0 116 2 3 17 18 31 0 1 2 3 1 0 16 17 18 31 bsdto(o) bsdti(i) 15 14 don't care 2 15 1 15 15 don't care 15:msb, 0:lsb 14 21 8 8 0 0 don't care figure 20. timing of i 2 s ? digital high pass filter the adc of stereo codec has a digital high pass filter for dc offset cancellation. the cut-off frequency of the hpf is 3.4hz (@fs=44.1khz) and scales with sampling rate (fs). the adc of mono codec also has a digital high pass filter for dc offset cancellation. the cut-off frequency of the hpf is 0.62hz (@bfs=8khz) and scales with sampling rate (bfs).
asahi kasei [ak4641] ms0301-e-00 2004/05 - 22 - ? mic input adc of stereo codec mic in 0db/+20db ipga with alc mono mixer p stereo mixer att aux in micad bit a uxad bit micl bit micm bit att dac of mono codec dac2 bit = ?0?: mic input signal ?1?: dac signal figure 21. microphone input the ak4641 has the following functions for mic input. (1) 1 st mic amplifier of 20db gain that can be selected on/off by ?mgain? bit. (2) 2 nd amplifier that has pga with alc. this volume is controlled by ?ipga6-0? bit as table 7. while alc is working, master clock must be present. when master clock is not provided or pmmic bit = ?0?, it is invalid to write to ?ipga6-0?. (3) attenuator for stereo mixer. this volume is controlled by ?atts2-0? bit as table 8. (4) attenuator for mono mixer. this attenuator level is 4db and this on/off is controlled by ?attm? bit. ipga6-0 gain (db) step 47h +27.5 46h +27.0 45h +26.5 : : 36h +19.0 : : 10h +0.0 default : : 06h ? 5.0 05h ? 5.5 04h ? 6.0 03h ? 6.5 02h ? 7.0 01h ? 7.5 00h ? 8.0 0.5db table 7. microphone input gain setting atts2-0 attenuation 7h ? 6db 6h ? 9db 5h ? 12db default 4h ? 15db 3h ? 18db 2h ? 21db 1h ? 24db 0h ? 27db table 8. attenuator table
asahi kasei [ak4641] ms0301-e-00 2004/05 - 23 - ? mic gain amplifier the ak4641 has a gain amplifier for microphone input. this gain is 0db or +20db, selected by the mgain bit. the typical input impedance is 30k ? . mgain bit input gain 0 0db 1 +20db default table 9. input gain ? mic power the mpi and mpe pins supply power for the microphone. these output voltages are 0.75 x avdd (typ) and the load resistance is 2k ? (min). no capacitor must be connected directly to mpi and mpe pins. mpwri/mpwre bit can control output from mpi and mpe pin. int ext mpi mpe dtmic bit mdt 0.075 x avdd mpwre bit mpwri bit 500k g m r l headset g r l headphone or ak4641 figure 22. microphone power supply and mic detection ? mic detection function the ak4641 includes the detection function of microphone. the external circuit is showed in figure 22. the followings show the example of external microphone detection sequence: (1) mpwre bit = ?1?. (2) mpe drives external microphone. (3) dtmic bit is set as table 10. in case of headset, th e input voltage of mdt pin is higher than 0.078 x avdd because of the relationship between the bias resistance at mpe pin (typ. 2.2k ? ) and the microphone impedance. in case of headphone, the input voltage of mdt pin is 0v because the pin of headphone jack connected to mdt pin is assigned as ground. input level of dtm dtmic result 0.078 x avdd 1 mic (headset) < 0.050 x avdd 0 no mic (headphone) table 10. microphone detection result
asahi kasei [ak4641] ms0301-e-00 2004/05 - 24 - ? manual mode the ak4641 becomes a manual mode at alc1 bit = ?0?. this mode is used in the case shown below. 1. after exiting reset state, set up the registers for the alc1 operation (ztm1-0, lmth and etc) 2. when the registers for the alc1 operation (limiter period, recovery period and etc) are changed. for example; when the change of the sampling frequency. 3. when ipga is used as a manual volume. ? mic-alc operation the alc (automatic level control) of mic input is done by alc1 block when alc1 bit is ?1?. [1] alc1 limiter operation when the alc1 limiter is enabled, and ipga output exceeds the alc1 limiter detection level (lmth), the ipga value is attenuated by the amount defined in the alc1 limiter att step (lmat1-0 bits) automatically. when the zelm bit = ?1?, the timeout period is set by the ltm1-0 bits. the operation for attenuation is done continuously until the input signal level becomes lmth or less. if the alc1 bit does not change into ?0? after completing the attenuation, the attenuation operation repeats while the input signal level equals or exceeds lmth. when the zelm bit = ?0?, the timeout period is set by th e ztm1-0 bits. this enables the zero-crossing attenuation function so that the ipga value is attenuated at the zero-detect points of the waveform. [2] alc1 recovery operation the alc1 recovery refers to the amount of time that the ak4641 will allow a signal to exceed a predetermined limiting value prior to enabling the limiting function. the alc1 recovery operation uses the wtm1-0 bits to define the wait period used after completing an alc1 limiter operation. if the input signal does not exceed the ?alc1 recovery waiting counter reset level?, the alc1 recovery operation starts. the ipga value increases automatically during this operation up to the reference level (ref6-0 bits). the alc1 recovery operation is done at a period set by the wtm1-0 bits. zero crossing is detected during wtm1-0 period, the alc1 recovery operation waits wtm1-0 period and the next recovery operation starts. during the alc1 recovery operation, when input signal level exceeds the alc1 limiter detection level (lmth), the alc1 recovery operation changes immediately into an alc1 limiter operation. in the case of ?(recovery waiting counter reset level) ipga output level < limiter detection level? during the alc1 recovery operation, the wait timer for the alc1 recovery operation is reset. therefore, in the case of ?(recovery waiting counter reset level) > ipga output level?, the wait timer for the alc1 recovery operation starts. the alc1 operation corresponds to the impulse noise. when the impulse noise is input, the alc1 recovery operation becomes faster than a normal recovery operation.
asahi kasei [ak4641] ms0301-e-00 2004/05 - 25 - [3] example of alc1 operation table 11 shows the examples of the alc1 setting. in case of this examples, alc1 operation starts from 0db. fs=8khz fs=16khz fs=44.1khz register name comment data operation data operation data operation lmth limiter detection level 1 ? 4dbfs 1 ? 4dbfs 1 ? 4dbfs ltm1-0 limiter operation period at zelm = 1 00 don?t use 00 don?t use 00 don?t use zelm limiter zero crossing detection 0 enable 0 enable 0 enable ztm1-0 zero crossing timeout period 00 16ms 01 16ms 10 11.6ms wtm1-0 recovery waiting period *wtm1-0 bits should be the same data as ztm1-0 bits 00 16ms 01 16ms 10 11.6ms ref6-0 maximum gain at recovery operation 47h +27.5db 47h +27.5db 47h +27.5db ipga6-0 gain of ipga at alc1 operation start 10h 0db 10h 0db 10h 0db lmat1-0 limiter att step 00 1 step 00 1 step 00 1 step ratt recovery gain step 0 1 step 0 1 step 0 1 step alc1 alc1 enable bit 1 enable 1 enable 1 enable table 11. example of the alc1 setting the following registers should not be changed during the alc1 operation. these bits should be changed, after the alc1 operation is finished by alc1 bit = ?0? or pmmic bit = ?0?. ? ltm1-0, lmth, lmat1-0, wtm1-0 , ztm1-0, ratt, ref6-0, zelm bits ipga gain at alc1 operation start can be changed from the default value of ipga6-0 bits while pmmic bit is ?1? and alc1 bit is ?0?. when alc1 bit is changed from ?1? to ?0?, ipga holds the last gain value set by alc1 operation. manual mode * the value of ipga should be the same or smaller than ref?s wr (ztm1-0, wtm1-0, ltm1-0) wr (ref6-0) wr (ipga6-0) alc1 o p eration wr (alc1= ?1?, lmat1-0, ratt, lmth, zelm) example: limiter = zero crossing enable recovery cycle = 16ms @ fs= 8khz limiter and recovery step = 1 maximum gain = +27.5db limiter detection level = ? 4dbfs (1) addr=08h, data=00h (2) addr=0ah, data=47h (4) addr=09h, data=21h (3) addr=0bh, data=10h * alc1 bit must be set to ?1? at more than zero cross time out period after the value of ipga is set (see figure 22). note : wr : write figure 23. registers set-up sequence at alc1 operation
asahi kasei [ak4641] ms0301-e-00 2004/05 - 26 - [setting timing of ipga and alc1 bits] ipga6-0 bits (2) (3) a h bh a h bh ipga a lc1 bit (5) ztm1-0 bits xxh 00h (1) (4) xxh t > zero cross time out period figure 24. setting timing of ipga and alc1 bits (1) set the zero cross time out period of ipga as 128/fs: ztm1-0 bits = ?00?. (note) (2) set the ipga value of alc1 operation start by ipga6-0 bits. (3) the value of ipga6-0 bits is reflected to actual gain at zero crossing or zero cross time out. (4) set the zero cross time out period of alc1 operation by ztm1-0 bits after the zero cross time out period set by (1). (5) set alc1 bit to ?1?. (note) if ztm1-0 bits are set to the value except for ?00?, alc1 bit must be set to ?1? after this zero cross time out period.
asahi kasei [ak4641] ms0301-e-00 2004/05 - 27 - ? dac of stereo codec mono mixer stereo mixer dac of stereo codec datt dacm bit smute 5 band equalizer dem dacl bit figure 25. dac block diagram of stereo codec the ak4641 has the following functions for dac of stereo codec. (1) 5 band equalizer (2) soft mute (3) digital attenuator (4) de-emphasis filter (32khz, 44.1khz and 48khz) ? de-emphasis filter the ak4641 includes the digital de-emphasis filter (tc = 50/15 s) by iir filter. setting the dem1-0 bits enables the de-emphasis filter. dem1 dem0 mode 0 0 44.1khz 0 1 off default 1 0 48khz 1 1 32khz table 12. de-emphasis control ? digital attenuator the ak4641 has a channel-independent digital attenuator (256levels, 0.5db step, mute). the attl/r7-0 bits set the attenuation level of each channel (table 13). when the da ttc bit = ?1?, the attl7-0 bits control both lch and rch attenuation levels. when the dattc bit = ?0?, the attl7-0 bits cont rol lch level and attr7-0 bits control rch level. this attenuator has a soft transition function. it takes around 1061/fs (24ms@44.1khz) at tm bit = ?0? and 256/fs (5.8ms@44.1khz) at tm bit = ?1? from 00h to ffh. attl/r7-0 attenuation 00h 0db default 01h ? 0.5db 02h ? 1.0db 03h ? 1.5db : : : : fdh ? 126.5db feh ? 127.0db ffh mute ( ? ) table 13. datt code table
asahi kasei [ak4641] ms0301-e-00 2004/05 - 28 - ? 5 band equalizer the ak4641 has 5 band equalizer before dac of stereo codec as shown in figure 25. the center frequencies and cut/boost amount are the followings. ? center frequency: 100hz, 250hz, 1khz, 3.5khz, 10khz (note 25, note 26) ? cut/boost amount: minimum ?10.5db, maximum +12db, step 1.5db note 25: these are the frequencies when the sampling frequency is 44.1khz. these frequencies are proportional to the sampling frequency. note 26: 100hz is not center frequency but the frequency component lower than 100hz is controlled. note 27: 10khz is not center frequency but the frequency component higher than 10khz is controlled. eq5 bit controls on/off of this equalizer and these b oost amount are set by eqx3-0 bit as shown in table 14. eqa3-0: select the boost level of 100hz eqb3-0: select the boost level of 250hz eqc3-0: select the boost level of 1khz eqd3-0: select the boost level of 3.5khz eqe3-0: select the boost level of 10khz eqx3-0 boost amount 0h +12.0db 1h +10.5db 2h +9.0db 3h +7.5db : : 8h 0db default : : dh ? 7.5db eh ? 9.0db fh ? 10.5db table 14. boost amount of 5 band equalizer
asahi kasei [ak4641] ms0301-e-00 2004/05 - 29 - ? soft mute soft mute operation is performed in the digital domain. when the smute bit goes to ?1?, the output signal is attenuated by ? (?0?) during the cycle set by the tm bit. when the smute bit is returned to ?0?, the mute is cancelled and the output attenuation gradually changes to the digital attenuator leve l of attl/r7-0 bits during th e cycle set by the tm bit. if the soft mute is cancelled within the cycle set by the tm bit after starting the operation, the attenuation is discontinued and returned to the digital attenuator level. the soft mute is effective for changing the signal source without stopping the signal transmission. table 15 shows the soft mute time when the digital attenuator level is 0db (attl/r7-0 bits = ?0?). as the digital attenuator level is less than 0db, the soft mute time becomes shorter. tm cycle 0 1061/fs default 1 256/fs table 15. soft mute time setting smute bit a ttenuation tm bit attl/r7-0 bits ? tm bit gd gd (1) (2) (3) a nalog output figure 26. soft mute function note: (1) the output signal is attenuated until ? (?0?) by the cycle set by the tm bit. (2) analog output corresponding to digital input has the group delay (gd). (3) if the soft mute is cancelled wit hin the cycle of setting the tm bit, the attenuation is discounted and returned to 0db(the set value).
asahi kasei [ak4641] ms0301-e-00 2004/05 - 30 - ? aux input stereo mixer volume a uxin+ auxl bit mixer for adc of stereo codec a uxad bit gn3-0 bits a uxin ? figure 27. aux input aux input is differential input at auxsi bit = ?0? and single end input at auxsi bit = ?1?. auxin+ pin should be used at single end input (auxsi bit = ?1?). the ak4641 has a volume for aux input. this volume is controlled by gn3-0 bits as shown in table 16. the switching nois e occurs when gn3-0 bits are changed. gn3-0 gain (db) fh +24.0 eh +21.0 dh +18.0 : : 7h +0.0 default : : 2h ? 15.0 1h ? 18.0 0h ? 21.0 table 16. aux input gain setting
asahi kasei [ak4641] ms0301-e-00 2004/05 - 31 - ? stereo line output (lout and rout pins) and mono line output (mout2 pin) att + dac of stereo codec mic in volume stereo line out a ux in 0db/+20db ipga att micl bit dacl bit auxl bit mono line out(mout2) external headphone amp external speaker amp dac of mono codec dac2 bit figure 28. stereo line output and mono line out2 line out path does not have volume but the attenuator of dac of stereo codec, volume of mic in and aux in control the output signal level. the ak4641 does not have mute circuits to remove pop noise at power up and down for line output. the signal of the stereo mixer is converted to a mono signal [(l+r)/2] and this signal is output via mout2 pin. ? mono line output (mout+/mout ? pin) dac of mono codec att + dac of stereo codec mic in 0db/+20db ipga mout+ 1/2 ? 17db/+6db 1/2 micm bit dacm bit mogn bit att mout ? dac2 bit figure 29. mono output mono mixer mixes signal from mic in, lch signal and rch signal from dac of stereo codec. this mixed signal is output from the mout+ and mout ? pins by differential output. amp for mono output has 6db gain and ? 17db gain that are set by the mogn bit.
asahi kasei [ak4641] ms0301-e-00 2004/05 - 32 - ? 16bit mono codec for bluetooth i/f the ak4641 has the 16bit mono codec to connect with bluetooth module that supports 8khz to 16khz sample rate. the ak4641 includes pll that generate the master clock for mono codec from input bsync signal. the pll should be powered-up after bsync signal is inputted. the pll needs 90ms (max) lock time, when the pll is powered-up (pmbif bit = ?0? ?1?) and bsync is input. pmda2 bit should be set to ?0? or ?0? data should be input to dac of mono codec during 90ms after pmbif bit is set to ?1?. bbick and bsync should always be present when either adc or dac of mono codec is power-up. if these clocks are not provided, the ak4641 may draw excess current and it is not possible to operate properly because utilizes dynamic refreshed logic internally. if bbick or bsync is not present, adc and dac of mono codec should be in the power-down mode. adc the adc of mono codec outputs the signal from dac of stereo codec, mic in and aux in. the adc of mono codec enters an initialization cycle that starts when the pmad2 bit is changed from ?0? to ?1?. the initialization cycle time is 1057/bfs, or 132ms@bfs=8khz. during the initialization cycle, the adc digital data output of mono codec are forced to a 2's compliment, ?0?. the adc output of mono codec reflects the analog input signal after the initialization cycle is complete. ? adc full scale level: 0.6*avdd [vpp](1.98vpp@3.3v) full scale level of adc of mono codec is the same as that of dac of stereo codec. att + stereo dac mic in 0db/+20db ipga att volume a ux in dacl bit auxl bit micl bit a dc of mono codec line out a k4641 external hp-amp bluetooth module headphone bth headset dac of mono codec adc2 bit dac2 bit figure 30. path to adc of mono codec dac the signal that is output from dac of mono codec is sent to line out, mono out and adc of stereo codec. ? dac full scale level: 0.6*avdd [vpp](1.98vpp@3.3v) full scale level of dac of mono codec is the same as that of adc of stereo codec. adc of stereo codec mic in 0db/+20db ipga with alc mono out p line out through stereo mixer att micad bit a ux in micl bit micm bit att bluetooth module bth headset dac of mono codec a k4641 microphone dac2 bit figure 31. path from dac of mono codec
asahi kasei [ak4641] ms0301-e-00 2004/05 - 33 - ? i 2 c-bus control interface the ak4641 supports the fast-mode i 2 c-bus (max: 400khz). 1. write operations figure 32 shows the data transfer sequence for the i 2 c-bus mode. all commands are preceded by a start condition. a high to low transition on the sda line while scl is high indicates a start condition (figure 38). after the start condition, a slave address is sent. this address is 7 bits long followed by an eighth bit that is a data direction bit (r/w). the most significant seven bits of the slave address ar e fixed as ?0010010?. if the slave address matches that of the ak4641, the ak4641 generates an acknowledge and the operation is executed. the master must generate the acknowledge-related clock pulse and release the sda line (high) during the acknowledge clock pulse (figure 39). a r/w bit value of ?1? indicates that the read operation is to be executed. a ?0? indicates that the write operation is to be executed. the second byte consists of the control register address of the ak4641. the format is msb first, and those most significant 3-bits are fixed to zeros (figure 34). the data af ter the second byte contains control data. the format is msb first, 8bits (figure 35). the ak4641 generates an acknowledge after each byte has been received. a data transfer is always terminated by a stop condition generated by the master. a low to high transition on the sda line while scl is high defines a stop condition (figure 38). the ak4641 can perform more than one byte write operation per sequence. after receipt of the third byte the ak4641 generates an acknowledge and awaits the next data. the master can transmit more than one byte instead of terminating the write cycle after the first data byte is transferred. after receiving each data packet the internal 5-bit address counter is incremented by one, and the next data is automatically taken into the next address. if the address exceeds 1fh prior to generating the stop condition, the address counter will ?ro ll over? to 00h and the previous data will be overwritten. the data on the sda line must remain stable during the high period of the clock. the high or low state of the data line can only change when the clock signal on the scl line is low (figure 40) except for the start and stop conditions. sda slave address s s t a r t r/w="0" a c k sub address(n) a c k data(n) a c k data(n+1) a c k a c k data(n+x) a c k p s t o p figure 32. data transfer sequence at the i 2 c-bus mode 0 0 1 0 0 1 0 r/w figure 33. the first byte 0 0 0 a4 a3 a2 a1 a0 figure 34. the second byte d7 d6 d5 d4 d3 d2 d1 d0 figure 35. byte structure after the second byte
asahi kasei [ak4641] ms0301-e-00 2004/05 - 34 - (2)-2. read operations set the r/w bit = ?1? for the read operation of the ak4641. after transmission of data, the master can read the next address?s data by generating an acknowledge instead of generating a stop condition after the receipt of the first data word. after receiving each data packet the internal 5-bit address counter is incremented by one, and the next data is automatically taken into the next address. if the address exceeds 1fh prior to generating a stop condition, the address counter will ?roll over? to 00h and the previous data will be overwritten. the ak4641 supports two basic read operations: current address read and random address read. (2)-2-1. current address read the ak4641 contains an internal address counter that maintains the address of the last word accessed, incremented by one. therefore, if the last access (either a read or write) were to address n, the next current read operation would access data from the address n+1. after receipt of the slave address with r/w bit set to ?1?, the ak4641 generates an acknowledge, transmits 1-byte of data to the address set by the internal address counter and increments the internal address counter by 1. if the master does not generate an acknowledge to the data but instead generates a stop condition, the ak4641 ceases transmission. sda slave address s s t a r t r/w="1" a c k a c k data(n+1) a c k data(n+2) a c k a c k data(n+x) a c k p s t o p data(n) figure 36. current address read (2)-2-2. random address read the random read operation allows the master to access any memory location at random. prior to issuing the slave address with the r/w bit set to ?1?, the master must first perform a ?dummy? write operation. the master issues a start request, a slave address (r/w bit = ?0?) and then the register address to read. after the register address is acknowledged, the master immediately reissues the start request and the slave address with the r/w bit set to ?1?. the ak4641 then generates an acknowledge, 1 byte of data and increments the internal address counter by 1. if the master does not generate an acknowledge to the data but instead generates a stop condition, the ak4641 ceases transmission. sda slave address s s t a r t r/w="0" a c k a c k a c k data(n) a c k data(n+x) a c k p s t o p sub address(n) s slave address r/w="1" s t a r t data(n+1) a c k a c k figure 37. random address read
asahi kasei [ak4641] ms0301-e-00 2004/05 - 35 - scl sda stop condition start condition s p figure 38. start and stop conditions scl from master acknowledge data output by transmitter data output by receiver 1 9 8 start condition not acknowledge clock pulse for acknowledgement s 2 figure 39. acknowledge on the i 2 c-bus scl sda data line stable; data valid change of data allowed figure 40. bit transfer on the i 2 c-bus
asahi kasei [ak4641] ms0301-e-00 2004/05 - 36 - ? register map addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h power management 1 pmvcm 0 0 pmlo pmmo pmaux pmmic pmadc 01h power management 2 mckpd 0 0 mckac pmmo2 0 0 pmdac 02h signal select1 mogn psmo dacm micm 0 0 0 psmo2 03h signal select2 dacl 0 au xl micl 0 auxsi pslol pslor 04h mode control 1 0 0 0 0 0 0 dif1 dif0 05h mode control 2 0 mck1 mck0 0 0 hpm loop 0 06h dac control 0 tm smute dattc 0 eq dem1 dem0 07h mic control 0 0 auxad mpwre mpwri micad msel mgain 08h timer select 0 0 ztm1 ztm0 wtm1 wtm0 ltm1 ltm0 09h alc mode control 1 0 0 alc1 zelm lmat1 lmat0 ratt lmth 0ah alc mode control 2 0 ref6 re f5 ref4 ref3 ref2 ref1 ref0 0bh input pga control 0 ipga6 ipga 5 ipga4 ipga3 ipga2 ipga1 ipga0 0ch lch digital att control attl7 attl6 attl5 attl4 attl3 attl2 attl1 attl0 0dh rch digital att control attr7 at tr6 attr5 attr4 attr3 attr2 attr1 attr0 0eh volume control attm atts2 atts1 atts0 gn3 gn2 gn1 gn0 0fh status 0 0 0 0 0 0 0 dtmic 10h eq control 250hz/100hz eqb3 eqb2 eqb1 eqb0 eqa3 eqa2 eqa1 eqa0 11h eq control 3.5khz/1khz eqd3 eqd2 eqd1 eqd0 eqc3 eqc2 eqc1 eqc0 12h eq control 10khz 0 0 0 0 eqe3 eqe2 eqe1 eqe0 13h bt i/f codec control 0 btfmt1 btfmt0 dac2 adc2 pmbif pmda2 pmad2 *pdn pin = ?l? resets the registers to their default values. *unused bits must contain a ?0? value. *only write to address 00h to 13h.
asahi kasei [ak4641] ms0301-e-00 2004/05 - 37 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h power management 1 pmvcm 0 0 pmlo pmmo pmaux pmmic pmadc r/w r/w rd rd r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 pmadc: adc block of stereo codec power control 0: power down (default) 1: power up when pmadc bit changes from ?0 ? to ?1?, initializing cycle (2081/ fs=47.2ms@44.1khz) starts. after initializing cycle, digital data of the adc of stereo codec is output. pmmic: mic in block power control 0: power down (default) 1: power up pmmo: mono out power control 0: power down (default) 1: power up pmlo: line out power control 0: power down (default) 1: power up pmaux: aux in power control 0: power down (default) 1: power up pmvcm: vcom block power control 0: power down (default) 1: power up
asahi kasei [ak4641] ms0301-e-00 2004/05 - 38 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 01h power management 2 mckpd 0 0 mckac pmmo2 0 0 pmdac r/w r/w rd rd r/w r/w rd rd r/w default 1 0 0 0 0 0 0 0 pmdac: dac block of stereo codec power control 0: power down (default) 1: power up pmmo2: mono out2 power control 0: power down (default) 1: power up mckac: master clock input mode select 0: c-mos input (default) 1: ac-coupling input mckpd: mclk input buffer control 0: enable 1: disable (default) when mclk input with ac coupling is stopped, mckpd bit should be set to ?1?. adc and dac of 16bit stereo codec are powered-down at mckpd bit = ?1?. note) the stereo mixer block (pmmix) is powered down automatically. pmlo=pmmo2=pmad2 bits = ?0?: power down others: power up each block can be powered down respectively by writing ?0? in each bit. when the pdn pin is ?l?, all blocks are powered down. when all bits except mckpd bit are ?0? in the 00h a nd 01h addresses, all blocks are powered down. the register values remain unchanged. ipga gain is reset when pmmic bit is ?0? (refer to the ipga6-0 bits description). when any of the blocks are powered up, the pmvcm bit must be set to ?1?. mclk, bick and lrck must always be present unless pmmic=pmadc=pmdac bits = ?0? or pdn pin = ?l?. bbick and bsync must always be present unless pmad2=pmda2=pmbif bits = ?0? or pdn pin = ?l?.
asahi kasei [ak4641] ms0301-e-00 2004/05 - 39 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 02h signal select1 mogn psmo dacm micm 0 0 0 psmo2 r/w r/w r/w r/w r/w rd rd rd r/w default 0 0 0 0 0 0 0 0 psmo2: select mono output 2 of mout2 pin (mixing = (l+r)/2) 0: power save mode. output vcom voltage. (default) 1: normal operation (note) hi-z is output at pmmo2 bit = ?0?. micm: switch control from mic in to mono mixer 0: off (default) 1: on dacm: switch control from dac of stereo codec to mono mixer (mixing = (l+r)/2) 0: off (default) 1: on psmo: select mono output of mout+/ ? pins 0: power save mode. output vcom voltage. (default) 1: normal operation (note) hi-z is output at pmmo bit = ?0?. mogn: gain control for mono output 0: +6db (default) 1: ? 17db
asahi kasei [ak4641] ms0301-e-00 2004/05 - 40 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 03h signal select2 dacl 0 aux l micl 0 auxsi pslol pslor r/w r/w rd r/w r/w rd r/w r/w r/w default 1 0 0 0 0 0 0 0 pslor: select rch line output of rout pin 0: power save mode. output vcom voltage. (default) 1: normal operation (note) hi-z is output at pmlo bit = ?0?. pslol: select lch line output of lout pin 0: power save mode. output vcom voltage. (default) 1: normal operation (note) hi-z is output at pmlo bit = ?0?. micl: switch control from mic in to stereo mixer 0: off (default) 1: on auxl: switch control from aux in to stereo mixer 0: off (default) 1: on dacl: switch control from dac of stereo codec to stereo mixer 0: off 1: on (default) auxsi: select aux input 0: differential input (default) 1: single-ended input. auxin+ pin is used for aux input and auxin ? pin is not available. addr register name d7 d6 d5 d4 d3 d2 d1 d0 04h mode control 1 0 0 0 0 0 0 dif1 dif0 r/w rd rd rd rd rd rd r/w r/w default 0 0 0 0 0 0 1 0 dif1-0: digital audio interface format select (see table 5.) addr register name d7 d6 d5 d4 d3 d2 d1 d0 05h mode control 2 0 mck1 mck0 0 0 hpm loop 0 r/w rd r/w r/w rd rd r/w r/w rd default 0 0 0 0 0 0 0 0 loop: loopback on/off 0: off (default) 1: on adc output data of stereo codec is inputted to both lch and rch of dac of stereo codec. hpm: mono output select from dac of stereo codec 0: stereo (default) 1: mono. (l+r)/2 signal is output from lch and rch of dac of stereo codec mck1-0: input master clock select (see table 2.)
asahi kasei [ak4641] ms0301-e-00 2004/05 - 41 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 06h dac control 0 tm smute dattc 0 eq dem1 dem0 r/w rd r/w r/w r/w rd r/w r/w r/w default 0 0 0 1 0 0 0 1 dem1-0: de-emphases response (see table 12.) eq: select 5 band equalizer. 0: off (default) 1: on dattc: dac of stereo codec digital attenuator control mode select 0: attl6-0 and attr6-0 bits control atte nuator level of lch a nd rch respectively. 1: attl6-0 bits contro l both lch and rch at same time. (default) when dattc bit = ?1?, the value of attr6-0 does not change. smute: soft mute control 0: normal operation (default) 1: dac outputs of stereo codec soft-muted tm: soft mute and datt transition time select (see table 15.) addr register name d7 d6 d5 d4 d3 d2 d1 d0 07h mic control 0 0 auxad mpwre mpwri micad msel mgain r/w rd rd r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 1 0 1 mgain: 1 st mic amp gain control 0: off. 0db 1: on. +20db (default) msel: microphone select 0: internal mic (default) 1: external mic micad: switch control from mic in to adc of stereo codec 0: off 1: on (default) mpwri: power supply control for internal microphone 0: off (default) 1: on mpwre: power supply for external microphone 0: off (default) 1: on
asahi kasei [ak4641] ms0301-e-00 2004/05 - 42 - auxad: switch control from aux in to adc of stereo codec 0: off (default) 1: on addr register name d7 d6 d5 d4 d3 d2 d1 d0 08h timer select 0 0 ztm1 ztm0 wtm1 wtm0 ltm1 ltm0 r/w rd rd r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 ltm1-0: alc1 limiter operation period at ze ro crossing disable (zelm bit = ?1?) the ipga value is changed immediately. when the ipga value is changed continuously, the change is done by the period specified by ltm1-0 bits. alc1 limiter operation period ltm1 ltm0 8khz 16khz 44.1khz 0 0 0.5/fs 63 s 31 s 11 s default 0 1 1/fs 125 s 63 s 23 s 1 0 2/fs 250 s 125 s 45 s 1 1 4/fs 500 s 250 s 91 s table 17. alc1 limiter opera tion period at zero crossing disable (zelm bit = ?1?) wtm1-0: alc1 recovery waiting period wtm1-0 bits set a period of recovery operation when an y limiter operation does not occur during alc1 operation. when the output signal level exceeds auto recovery waiting counter reset level set by lmth bit, the auto recovery waiting counter is reset. the waiting timer starts when the output signal level becomes below the auto recovery waiting counter reset level. alc1 recovery operation waiting period wtm1 wtm0 8khz 16khz 44.1khz 0 0 128/fs 16ms 8ms 2.9ms default 0 1 256/fs 32ms 16ms 5.8ms 1 0 512/fs 64ms 32ms 11.6ms 1 1 1024/fs 128ms 64ms 23.2ms table 18. alc1 recovery operation waiting period ztm1-0: zero crossing timeout at the write operation by p, alc1 recovery operation and zero crossing enable (zelm bit = ?0?) of the alc1 operation when ipga of each l/r channels perform zero crossing or timeout independently, the ipga value is changed by p write operation or alc1 rec overy operation or alc1 limite r operation (zelm bit = ?0?). zero crossing timeout period ztm1 ztm0 8khz 16khz 44.1khz 0 0 128/fs 16ms 8ms 2.9ms default 0 1 256/fs 32ms 16ms 5.8ms 1 0 512/fs 64ms 32ms 11.6ms 1 1 1024/fs 128ms 64ms 23.2ms table 19. zero crossing timeout period
asahi kasei [ak4641] ms0301-e-00 2004/05 - 43 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 09h alc mode control 1 0 0 alc1 zelm lmat1 lmat0 ratt lmth r/w rd rd r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 lmth: alc1 limiter detection level / recovery waiting counter reset level the alc1 limiter detection level and the alc1 recovery counter reset level may be offset by about 2db. lmth alc1 limiter detection level alc1 re covery waiting co unter reset level 0 adc input ? 6.0dbfs ? 6.0db > adc input ? 8.0dbfs default 1 adc input ? 4.0dbfs ? 4.0db > adc input ? 6.0dbfs table 20. alc1 limiter detection level / recovery waiting counter reset level ratt: alc1 recovery gain step during the alc1 recovery operation, the number of steps changed from current ipga value is set. for example, when the current ipga value is ?30h? and ratt bit = ?1? is set, ipga changes to ?32h? by the alc1 recovery operation, the output signal level is gained up by 1db (=0.5db x 2). when the ipga value exceeds the reference level (ref6-0 bits), the ipga value does not increase. ratt gain step 0 1 default 1 2 table 21. alc1 recovery gain step setting lmat1-0: alc1 limiter att step during the alc1 limiter operation, when either lch or rch exceeds the alc1 limiter detection level set by lmth, the number of steps attenuated from the current ipga value is set. for example, when the current ipga value is 47h and the lmat1-0 bits = ?11?, the ipga transition to ?43h? when the alc1 limiter operation starts, resulting in the input signal level be ing attenuated by 2db (=0. 5db x 4). when the attenuation value exceeds ipga = ?00h? ( ? 8db), it clips to ?00h?. lmat1 lmat0 att step 0 0 1 default 0 1 2 1 0 3 1 1 4 table 22. alc1 limiter att step setting zelm: enable zero crossing dete ction at alc1 limiter operation 0: enable (default) 1: disable when the zelm bit = ?0?, the ipga of each l/r channe l perform a zero crossing or timeout independently and the ipga value is changed by the alc1 operation. the zero crossing timeout is the same as the alc1 recovery operation. when the zelm bit = ?1?, the ipga value is changed immediately. alc1: alc1 enable 0: alc1 disable (default) 1: alc1 enable
asahi kasei [ak4641] ms0301-e-00 2004/05 - 44 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 0ah alc mode control 2 0 ref6 re f5 ref4 ref3 ref2 ref1 ref0 r/w rd r/w r/w r/w r/w r/w r/w r/w default 0 0 1 1 0 1 1 0 ref6-0: set the reference value at alc1 recovery operation during the alc1 recovery operation, if the ipga value exceeds the setting reference value by gain operation, then the ipga does not become larger than the reference value. for example, when ref6-0 bits = ?30h?, ratt = 2step, ipga = ?2fh?, even if the input signal does not exceed the ?alc1 recovery waiting counter reset level?, the ipga does not change to ?2fh? + 2step = ?31h?, but keeps ?30h?. default is ?36h?. ref6-0 gain (db) step 47h +27.5 46h +27.0 45h +26.5 : : 36h +19.0 default : : 10h +0.0 : : 06h ? 5.0 05h ? 5.5 04h ? 6.0 03h ? 6.5 02h ? 7.0 01h ? 7.5 00h ? 8.0 0.5db table 23. setting reference valu e at alc1 recovery operation addr register name d7 d6 d5 d4 d3 d2 d1 d0 0bh input pga control 0 ipga6 ip ga5 ipga4 ipga3 ipga2 ipga1 ipga0 r/w rd r/w r/w r/w r/w r/w r/w r/w default 0 0 0 1 0 0 0 0 ipga6-0: input analog pga (see table 7.) when ipga gain is changed, ipga6-0 bits should be written while pmmic bit is ?1? and alc1 bit is ?0?. ipga gain is reset when pmmic bit is ?0?, and then ipga operation starts from the default value when pmmic is changed to ?1?. when alc1 bit is changed from ?1? to ?0?, ipga holds the last gain value set by alc1 operation. when ipga6-0 bits are read, the register values written by the last write opera tion is read out regardless the actual gain. addr register name d7 d6 d5 d4 d3 d2 d1 d0 0ch lch digital att control attl7 attl6 attl5 attl4 attl3 attl2 attl1 attl0 0dh rch digital att control attr7 attr6 attr5 attr4 attr3 attr2 attr1 attr0 r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 attl/r7-0: digital att output control these bits control the attenuation level of dac output of stereo codec. step size of att is approximately 0.5db (see table 13). note) even if dattc bit = ?1?, attr7-0 bits are not changed whe n the attl7-0 bits are written.
asahi kasei [ak4641] ms0301-e-00 2004/05 - 45 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 0eh volume control attm at ts2 atts1 atts0 gn3 gn2 gn1 gn0 r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 1 0 1 0 1 1 1 gn3-0: volume of aux in (see table 16.) atts2-0: attenuator select of signal from mic in to stereo mixer (see table 8.) attm: attenuator control for signal from mic in to mono mixer 0: 0db (default) 1: ? 4db addr register name d7 d6 d5 d4 d3 d2 d1 d0 0fh status 0 0 0 0 0 0 0 dtmic r/w rd rd rd rd rd rd rd rd default 0 0 0 0 0 0 0 0 dtmic: microphone detection result 0: microphone is not detected. (default) 1: microphone is detected. addr register name d7 d6 d5 d4 d3 d2 d1 d0 10h eq control 250hz/100hz eqb3 eqb2 eqb1 eqb0 eqa3 eqa2 eqa1 eqa0 11h eq control 3.5khz/1khz eqd3 eqd2 eqd1 eqd0 eqc3 eqc2 eqc1 eqc0 r/w r/w r/w r/w r/w r/w r/w r/w r/w default 1 0 0 0 1 0 0 0 addr register name d7 d6 d5 d4 d3 d2 d1 d0 12h eq control 10khz 0 0 0 0 eqe3 eqe2 eqe1 eqe0 r/w rd rd rd rd r/w r/w r/w r/w default 0 0 0 0 1 0 0 0 eqa3-0: select the boost level of 100hz eqb3-0: select the boost level of 250hz eqc3-0: select the boost level of 1khz eqd3-0: select the boost level of 3.5khz eqe3-0: select the boost level of 10khz see table 14.
asahi kasei [ak4641] ms0301-e-00 2004/05 - 46 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 13h bt i/f codec control 0 btfmt1 btfmt0 dac2 adc2 pmbif pmda2 pmad2 r/w rd r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 1 0 0 0 pmad2: adc block of mono codec power control 0: power down (default) 1: power up pmda2: dac block of mono codec power control 0: power down (default) 1: power up pmbif: 16bit mono interface and pll block power control 0: power down (default) 1: power up adc and dac of 16bit mono codec are powered-down at pmbif bit = ?0?. ad2: select signal that is input to adc of 16bit mono codec 0: off 1: on (default) dac2: select dac of mono codec signal (see figure 21.) 0: mic input signal (default) 1: dac signal of mono codec btfmt1-0: digital audio interface format select for 16bit mono codec (see table 6.)
asahi kasei [ak4641] ms0301-e-00 2004/05 - 47 - system design figure 41 shows the system connection diagram for t the ak4641. 0.1 0.1 10 2.2 0.1 0.1 10 analog supply 2.6~ 3.6v mpe 1 2 3 4 5 6 7 8 9 mpi int vcom avss avdd pvdd pvss vcoc 27 20 19 rout dvss dvdd pdn tst1 scl sda sdti sdto lrck bick mclk reset dsp and up top view 5.1k ? 470n 1 2.2k 1 2.2k 1 c c 1 1 c c 26 mout2 c 25 tst2 10 24 bbick 23 bsync 22 bsdto 21 bsdti bluetooth proccesor ext mdt micout ain auxin+ auxin- mout+ mout- lout 36 35 34 33 32 31 30 29 28 10 11 12 13 14 15 16 17 18 notes: - avss, dvss and bvss of the ak4641 should be distributed separately from the ground of external controllers. - values of r and c in figure 41 should depend on system. - all digital input pins should not be left floating. figure 41. typical connection diagram
asahi kasei [ak4641] ms0301-e-00 2004/05 - 48 - 1. grounding and power supply decoupling the ak4641 requires careful attention to power supply and grounding arrangements. avdd, dvdd and bvdd are usually supplied from the system?s analog supply. if avdd, dvdd and bvdd are supplied separately, the power up sequence is not critical. avss, dvss and bvss of the ak4641 should be connected to the analog ground plane. system analog ground and digital ground should be connected together near to where the supplies are brought onto the printed circuit board. decoupling capacitors should be as near to the ak4641 as possible, with the small value ceramic capacitor being the nearest. 2. voltage reference vcom is a signal ground of this chip. a 2.2 f electrolytic capacitor in parallel with a 0.1 f ceramic capacitor attached to the vcom pin eliminates the effects of high frequency noise. no load current may be drawn from the vcom pin. all signals, especially clocks, should be kept away from the avdd and vcom pins in order to avoid unwanted coupling into the ak4641. 3. analog inputs the ak4641 has the 16bit mono codec to connect with bluetooth module that supports 8khz to 16khz sample rate. the ak4641 includes pll that generate the master clock for mono codec from input bsync signal. the pll should be powered-up after bsync signal is inputted. the pll needs 90ms (max) lock time, when the pll is powered-up (pmbif bit = ?0? ?1?). the mic inputs are single-ended. aux input is differential. th e input signal range scales with nominally at 0.06 x avdd vpp for the mic input, 0.6 x avdd vpp for aux input, centered around the internal common voltage (0.45 x avdd). usually the input signal is ac coupled using a capacitor. the cut-off frequency is fc = (1/2 rc). the ak4641 can accept input voltages from avss to avdd. 4. analog outputs the input data format for the dac of both stereo and mono codec is 2?s complement. the output voltage is a positive full scale for 7fffh(@16bit) and a negative full scale for 8000h(@16bit). mono output from the mout2 pin, mono line output from the mout+/mout ? pins and stereo line out from the lout/rout pins are centered at 0.45 x avdd.
asahi kasei [ak4641] ms0301-e-00 2004/05 - 49 - package 36pin qfn (unit: mm) 6.20 0.1 19 6.20 0.1 6.00 0.05 6.00 0.05 0.05 0.90 0.05 36 28 27 19 10 18 10 18 19 27 36 28 1 9 45 45 3 - c0.5 0.22 0.05 0.50 c0.7 0 . 2 2 0 . 0 5 3 - 0 . 4 8 0 . 1 1 0 . 3 4 0 . 1 1 0.60 0.01 0.22 0.05 0.02+0.02 -0.015 0.05 m note) the part of black at four corners on reverse side must not be soldered and must be open. ? material & lead finish package molding compound: epoxy lead frame material: cu lead frame surface treatm ent: solder plate (pb free)
asahi kasei [ak4641] ms0301-e-00 2004/05 - 50 - marking 1 4641vn xxxxxxx akm xxxxxxx : date code identifier (7 digits) revision history date (yy/mm/dd) revision reason page contents 04/05/17 00 first edition
asahi kasei [ak4641] ms0301-e-00 2004/05 - 51 - important notice ? these products and their specifications are subject to change without notice. before considering any use or application, consult the asahi kasei microsystems co., ltd. (akm) sales office or authorized distributor concerning their current status. ? akm assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. ? any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. ? akm products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and akm assumes no responsibility relating to any such use, except with the express written consent of the representative director of akm. as used here: a. a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. b. a critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. ? it is the responsibility of the buyer or distributor of an akm product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold akm harmless from any and all claims arising from the use of said product in the absence of such notification.

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